I2S_CCR

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Interpret as I2S_CCR

WSS=Val_0x0, SCLKG=Val_0x0

Description

Clock Configuration Register

Fields

SCLKG

This bit field is used to program the gating of SCLK. The programmed gating value must be less than or equal to the largest configured (programmed) audio resolution to prevent the truncating of RX/TX data. The I2S Clock Generation block must be disabled (I2S_CER[CLKEN] = 0x0) before making any changes in this value.

0 (Val_0x0): Clock gating is disabled

1 (Val_0x1): Gating after 12 SCLK cycles

2 (Val_0x2): Gating after 16 SCLK cycles

3 (Val_0x3): Gating after 20 SCLK cycles

4 (Val_0x4): Gating after 24 SCLK cycles

WSS

This bit field is used to program the number of SCLK cycles for which the word select line (WS_OUT) stays in the left or right sample mode. The I2S Clock Generation block must be disabled (I2S_CER[CLKEN] = 0x0) prior to any changes in this value.

0 (Val_0x0): 16 SCLK cycles

1 (Val_0x1): 24 SCLK cycles

2 (Val_0x2): 32 SCLK cycles

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